Metrology tasks in quantum computing

In superconducting quantum processors, a large share of energy loss originates at material interfaces: the native oxides and microscopic defects at metal–air, metal–substrate and substrate–air boundaries act as parasitic two-level systems that drain qubit coherence. Surface roughness amplifies the problem—more effective surface area means more oxide, more defect sites, more loss. Ion traps face a related issue: motional heating of trapped ions scales strongly with electrode surface condition.

Quantum devices are full of small, functional 3D structures: etched trenches in coplanar waveguide circuits, photonic waveguides where sidewall and surface roughness directly set scattering losses, microfabricated trap electrodes with critical edge and step geometries. Here, the questions are dimensional: Is the etch depth on target? Is the step height uniform? Are edges clean?

Scaling beyond a few hundred qubits pushes processor architectures into the third dimension: qubit chips are flip-chip bonded to wiring or interposer chips via indium bump arrays, with chip-to-chip gaps of only a few micrometers. Gap variation across the die shifts qubit frequencies and coupling strengths—so bump height uniformity and chip flatness before bonding decide device yield.

Underneath the nanoscale physics sits a classic precision-engineering task: substrates, carriers and interposers must be flat. Wafer bow, total thickness variation and warp propagate into every subsequent process step—from lithography focus to bonding gaps.

Often overlooked: quantum processors operate inside dilution refrigerators at millikelvin temperatures, where thermal contact between mating surfaces is everything. Thermal boundary resistance depends directly on the flatness and roughness of cold-stage interfaces, and vacuum integrity depends on sealing surface quality. A leaking flange or a poorly seated thermal joint costs days of cooldown time.